This invention relates to a semiconductor device and a method of making the semiconductor device.
Semiconductor devices such as Metal Insulator Semiconductor Field Effect Transistors (MISFETs), and more particularly Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are being produced with ever decreasing dimensions, in an effort to increase the number of such devices that can be produced in a given area of semiconductor substrate. The critical dimension in a typical MOSFET is the length of the channel region, which extends between the source region and the drain region of the device, at a major surface of the substrate. Hereinafter, this dimension is referred to as the gate length Lg.
In larger devices, the threshold voltage is largely independent of Lg. However, it is well known that as Lg is reduced, Short Channel Effects (SCEs) and Drain Induced Barrier Lowering (DIBL) become prominent, and can inhibit optimal performance of the device. Typically, these effects manifest themselves as a drop in threshold voltage Vth. This drop in Vth is more commonly referred to as Vth roll-off.
Physically, these effects can be explained by the electrostatic influence of the S/D regions (SCE) or an applied voltage on the drain (DIBL) on the channel region in very small devices, lowering the energy barrier for electrons or holes in the channel when the transistor is switched off (gate voltage zero), thus leading to higher off currents.
A number of ways of mitigating against SCEs such as DIBL have been developed. These include high effective channel doping and in particular, in smaller devices, the provision of pocket implants adjacent the source and drain regions (also known as halo implants). These approaches seek to locally modify (in the vicinity of the gate edge) the effective doping within the channel region of the device, and thereby maintain the gate voltage that is required to produce inversion within the channel. As a consequence the effective channel doping increases with decreasing channel length, raising the threshold voltage and thus leading to a counter effect to the SCE and DIBL.
However, these solutions have a number of disadvantages or problems associated therewith. The introduction of dopants into the channel region of the device generally leads to increased Coulomb scattering within the channel region, thereby reducing carrier mobility. Moreover, the large voltage barrier that is present between the source and drain regions and their associated pocket implants can lead to band-to-band tunnelling, which in turn leads to undesirable off-state leakage in the device.
Another known way of selectively controlling inversion within the channel region to compensate for SCE and DIBL is to provide a device that has a gate electrode with a work function that varies along the length of the channel. In particular, the value of the work function can be greater at the extremities of the gate than in the centre of the gate for NMOS transistors and smaller for PMOS transistors.
Such an inhomogeneous work function leads to a positive shift of the threshold voltage for NMOS devices whereas for PMOS devices this shift will be negative for decreasing gate lengths. In both cases, when the gate length is reduced, this trend is opposed to the SCE and DIBL effect which helps to achieve a desired flat curve of the threshold voltage versus the gate length.
EP1961038 describes a MOS transistor including a gate having a bottom part in contact with the gate oxide. The bottom part has an inhomogeneous work function along the length of the gate between the source and drain regions, the value of the work function being greater (smaller) at the extremities of the gate than in the centre of the gate for NMOS (PMOS). The gate comprises a first material in the centre and a second material in the remaining part. In EP1961038, this configuration is obtained by partial silicidation.